The cost of an SiC substrate depends on how many qualified wafers a single crystal growth run can ultimately deliver. Crystal growth, orientation and shaping, slicing, grinding, CMP, and cleaning progressively transmit material losses and quality requirements; low saw loss, low damage, and a clean surface must be jointly optimized. In addition to crystal size, material utilization also depends on crystal polytype, electrical properties, defects, and the usable volume after shaping; the number of qualified wafers after slicing is the denominator for cost accounting. The thickness budget: the material pitch per wafer is approximately equal to the sum of the final thickness, the total removal amount in subsequent processing, and the slicing loss. The benefit of a narrower saw kerf may be offset by additional damage removal. Surface acceptance: thickness and TTV, global warp, local roughness, scratches, and contamination are measured separately; a mirror-like appearance cannot replace full-wafer quality inspection.
1. Crystal growth determines the quality of material that downstream processes can work with
To manufacture an SiC substrate, the first step is to obtain a single crystal with the target polytype, electrical properties, and defect level. Taking 4H conductive SiC, commonly used for power devices, as the main line, physical vapor transport (PVT) is the mature industrialization route. Here the process is consolidated into six main modules, with chamfering, annealing, in-process cleaning, and inspection interspersed; the endpoint is a bare substrate ready for subsequent epitaxy.
In a PVT furnace, powder sublimates in a hotter zone, and the vapor phase transports to near the relatively cooler seed crystal where it crystallizes. Defects and the shaping removal zone are shown schematically. PVT grows crystals through vapor transport: high-purity SiC powder is placed at the bottom of a graphite crucible, with the seed crystal above. Under high temperature and low pressure, the raw material sublimates to form vapor-phase components containing silicon and carbon, which are transported to near the seed crystal driven by temperature gradients and concentration differences, and then recrystallize to form a single crystal. The thermal field, pressure, and raw material state need to maintain a suitable evolution during growth in order to balance growth rate, interface morphology, and polytype stability.
Polytype, dislocations, and electrical properties determine the usable range. Heteropolytype inclusions, micropipes, dislocations, and cracks are different defects, and their impact on usable area and downstream device risk also differs. Conductive products also require control of doping and resistivity distribution. As crystal diameter and length increase, only by simultaneously maintaining qualified regions can the number of deliverable substrates increase; bulk crystal defects are mainly managed through growth control and sorting management.
Growth efficiency must be reflected in qualified output of the same specification. Accelerating growth can reduce the furnace time occupied per unit crystal, but if defects, stress, or unqualified regions increase accordingly, downstream sorting losses will also expand. Tianyue Advanced's publicly disclosed process description emphasizes PVT condition control and downstream damage transmission, indicating that growth and processing must be linked around final specifications. When evaluating this stage, one should look at the effective output and quality distribution of crystals of the same specification.
2. Orientation and shaping establish crystal orientation, dimensions, and the slicing reference
The grown crystal still needs irregular portions removed, crystal orientation measured, end faces and outer diameter trimmed, and a slicing clamping reference established. This module converts the material obtained from growth into an ingot that can be processed in the specified posture and dimensions, while generating head and tail and edge material losses, directly changing the usable length and diameter for the next step.
The off-cut angle is the angle between the wafer surface normal and the crystal c-axis, and is controlled separately from edge chamfering. 4° is a common example for conductive 4H products; the specific value depends on product specifications. X-ray orientation transfers crystal orientation to the processing fixture. SiC has crystal anisotropy, and crystal orientation and off-cut angle affect subsequent epitaxial step structure and processing behavior. Conductive 4H products often use a small off-cut relative to the basal plane; for example, some Wolfspeed 150 mm and 200 mm product specifications use a 4° off-cut. Orientation measurement, end-face trimming, bonding, and mounting must jointly ensure the target cut plane; accurately measuring the angle alone still requires correct transfer to the slicing posture.
Edge rounding, end faces, and positioning marks each carry dimensional tasks. Outer diameter processing controls diameter, end-face processing establishes a reference, and positioning flats or notches help identify crystal orientation and mounting direction. Positioning marks and protective edge chamfering are different geometric requirements. Insufficient trimming leaves dimensional or edge problems, while excessive trimming consumes material that has already incurred growth cost; therefore, the margin must be determined in combination with the crystal quality map and product dimensions.
Shaping losses occur before wafer count. The usable length in cost accounting should start from the crystal after head and tail trimming and necessary sorting are completed. Estimating wafer output from the length of the whole rough crystal would count portions that must necessarily be removed later as output. Tianyue Advanced's publicly disclosed processing project materials list outer periphery rounding, flat processing, positioning flat processing, and wire slicing separately, reflecting these reference-establishment steps.
3. Slicing allocates material among saw loss, wafer thickness, and damage
Slicing divides the ingot into thin wafers while consuming material and leaving surface damage to be removed. Each wafer needs to reserve thickness for subsequent grinding and polishing; therefore, judging slicing economics requires considering the actual saw kerf, post-cut damage, thickness variation, chipping, and fracturing together. Diamond wire cutting and laser internal modification separation are different slicing routes. In the pitch model, slicing loss should also include the allocated ingot repair removal, while subsequent wafer surface processing allowance is calculated separately.
Reducing wire diameter requires maintaining stable cutting. Diamond wire uses abrasive grains to cut into hard and brittle SiC; the actual saw kerf is jointly affected by wire diameter, abrasive protrusion, wire movement, and cutting state. Fine wire can reduce material consumption, but tension, vibration, abrasive retention, and chip removal need to be coordinated. Gaoche GC-SCDW8300 publicly adopts adjustable axis spacing, workpiece swinging, dedicated diamond wire, and tension control, targeting 6–8 inch crystal cutting; its technical combination reflects the necessity of equipment and consumable coordination.
Cutting damage translates into subsequent removal amount. Saw marks, local thickness deviation, and subsurface microcracks need to be repaired downstream. If cutting load is increased solely to raise cutting speed, deeper damage may require a thicker slicing allowance and increase grinding time. Local chipping and fracturing directly reduce the number of wafers that can continue to be processed. The goal of slicing cost reduction is to reduce material and time consumption across the entire route under the constraint of yield.
Laser separation changes the composition of material loss. DISCO's KABRA forms a modified separation layer at a specified depth inside the ingot, and then separates the wafer from that layer. It replaces part of the material removal of traditional sawing with internal modification and separation, but the separation surface and the remaining ingot still require subsequent conditioning. When comparing the two routes, wafer surface repair, ingot reprocessing, and breakage must be included in total loss, and wafer output compared according to final specifications.
4. Grinding corrects geometric morphology and reduces the damage burden borne by CMP
After slicing, the wafer needs saw marks removed, thickness and parallelism adjusted, and major processing damage repaired. Grinding, lapping, thinning, and mechanical pre-polishing can be combined according to the route; the core task is to establish geometric morphology with relatively high efficiency and then leave a controllable shallow removal burden for subsequent CMP. Coarse grinding and fine grinding usually progressively reduce damage depth, while each may introduce new processing damage. TTV and Warp respectively express thickness consistency and global warp; the cross-sections in the figure are enlarged schematics.
While removing old damage, new damage must be controlled. Hard and brittle materials may undergo local brittle fracture under abrasive action. Coarse processing has a higher removal rate and may also leave new microcracks and disturbed layers; fine processing needs to reduce per-grain action and damage depth. The coordination of coarse and fine steps should be based on damage depth and the final thickness budget; switching to CMP too early prolongs polishing, while excessive grinding consumes material.
TTV, global warp, and roughness are controlled separately. TTV is the difference between the maximum and minimum thickness across the whole wafer, Warp reflects the overall warp range of the wafer median surface, and local surface roughness describes smaller-scale undulations. Some Wolfspeed 200 mm conductive product listings give TTV ≤ 5 μm and Warp ≤ 20 μm, indicating that delivery must simultaneously constrain multiple morphological indicators. These values belong to specific product specifications, and the measurement state and edge exclusion rules also need to match.
Double-sided processing relies on the coordination of motion, carrier, and abrasive. Double-sided grinding organizes relative motion through structures such as upper and lower plates and carrier gears; abrasive, pressure, plate surface condition, and carrier conditions jointly affect uniformity. Yujing YJ-16B5LC explicitly covers double-sided grinding of SiC wafers, using separate drives for the upper plate, lower plate, internal gear ring, and sun gear. This structure facilitates adjustment of processing motion, but the final effect is still determined by the specific process combination.
Damage control connects material utilization and polishing capacity. When the CMP target removal rate is similar, the deeper the damage remaining after grinding, the more material and time polishing needs to remove and occupy. Improvements on the grinding side can therefore simultaneously reduce thickness allowance and CMP load. For a production line, this is closer to final cost than merely comparing how many wafers per hour a single grinding machine processes.
5. Chemical mechanical polishing converts controllable damage into a pre-epitaxy surface
After geometric shaping is completed, CMP needs to further reduce roughness and residual processing damage to obtain a surface meeting pre-epitaxy requirements. SiC is hard and chemically stable; relying solely on strong mechanical action tends to increase scratches. Chemical mechanical polishing establishes a window between removal rate and surface integrity through the synergy of surface reaction and abrasive removal. SiC CMP generally forms and removes a surface modified layer through the synergy of reactive components and abrasives. The figure shows a general mechanism and does not correspond to a single slurry formulation; different crystal faces and equipment conditions need to be matched separately.
Reaction layer generation and removal need to match each other. Reactive components in the polishing liquid change the state of the outermost surface, and the abrasive and polishing pad then remove it, after which the newly exposed surface continues to react. If the surface reaction is too slow, the removal rate is limited; if abrasive agglomeration, local load, or pad surface condition gets out of control, scratches and non-uniformity may occur. The chemical reactions and removal behavior of different polar crystal faces of the wafer also need to be matched separately.
The upstream allowance determines how long CMP must work. At the same stable removal rate, the greater the thickness that must be removed, the longer the required processing time. Entegris's publicly disclosed SiC solution considers front-end grinding damage, slurry, polishing pad, filtration, and post-cleaning together, because these parts jointly determine surface quality and processing time. Simply increasing polishing pressure may offset removal rate gains with newly introduced defects.
Mirror-like appearance needs quantitative inspection added. AFM can measure local roughness, but when comparing values, Ra or Rq, scan range, sampling, and data processing methods need to be unified. Local scan results also need to be combined with full-wafer scratch, particle, and morphology inspection. The polished bare substrate can be used for subsequent epitaxy; the epitaxial layer thickness, doping, and defect control required by devices belong to the next manufacturing stage.
6. Cleaning removes processing residues and protects the surface quality already achieved
CMP introduces abrasive, reaction product, and organic component residues, and upstream steps may also bring metal and other contamination. Cleaning must remove these residues from the surface and reduce redeposition and recontamination during rinsing, drying, inspection, and packaging, so as to preserve the surface quality achieved through multiple processing steps. Brush cleaning, chemical cleaning, rinsing, and drying are typical process combinations. Different contamination types have different removal mechanisms; dislocations and deep processing damage are controlled by upstream quality control.
Particles, metals, and organics use different removal mechanisms. Particle removal involves surface detachment, liquid transport, and dispersion stability; metal contamination requires matching chemical mechanisms such as dissolution or complexation; organic and slurry residues require suitable formulations. Brush cleaning, acoustic assistance, and chemical liquids can be combined, but excessive intensity may increase surface risk. Therefore, cleaning formulation and physical action must be selected together.
Rinsing and drying determine whether residues can truly leave. After contamination detaches from the surface, if drainage and rinsing are insufficient, it may still redeposit. Ultrapure water, filtration, brush condition, and the drying process affect final particles and watermarks. Entegris has cleaning chemicals specifically for SiC processing residues, while Huahai Qingke's HSC-S1300 supports front and back side brush cleaning and acid/alkali cleaning compatibility in compound semiconductor cleaning, respectively reflecting the coordination of materials and equipment.
Delivery inspection separately judges surface and bulk quality. Final acceptance must combine morphology, roughness, scratches, particles, and contamination indicators, and retain crystal and processing batch traceability. A clean surface is beneficial for epitaxy preparation, but growth dislocations and unremoved deep damage still require corresponding inspection and upstream control. The cost benefit of cleaning is reducing scrap and rework of already completed high-value wafers at the final stage.
Cost accounting puts the six modules back into the same material and yield budget
Connecting the six stages, the core question is how many qualified wafers of the same specification a segment of usable crystal can form. Let the final wafer thickness be t, the total removal amount for front and back grinding and polishing after slicing be a, and the slicing loss allocated per wafer be k; then the material pitch is approximately p = t + a + k. The usable length H divided by p, rounded down, gives the theoretical wafer output in the simplified model.
The calculation uses a usable length of 20 mm and a final thickness of 350 μm to compare different slicing losses and subsequent removal amounts. All are example parameters, ignoring end corrections and sorting losses.
Reducing slicing loss: the benefit needs to reach the finished thickness. Using a usable length of 20 mm and a final thickness of 350 μm: when a is 80 μm and k is 170 μm, the pitch is 600 μm, and the theoretical output is 33 wafers; if k drops to 70 μm and a remains 80 μm, the pitch drops to 500 μm, and the theoretical output is 40 wafers. The reduction in material loss is thus converted into more wafers.
Increased damage can offset the benefit of low saw loss. If the slicing loss is reduced to 70 μm but the subsequent removal amount a must be increased from 80 μm to 180 μm, the pitch returns to 600 μm, and the theoretical wafer output returns to 33. This example shows that evaluating fine wire or new separation technologies requires simultaneously measuring the damage repair allowance behind them in order to judge the material utilization of the entire route.
Final cost also depends on the number of qualified wafers of the same specification. After theoretical output, losses caused by fracturing, crystal sorting, morphology, and unqualified surface quality must also be deducted. Only by dividing the total growth and processing cost by the final qualified wafer count can one approach the unit manufacturing cost of substrates of the same specification. Reducing furnace time, saw loss, or polishing time each has an effect; the most valuable optimization is to preserve material and time savings through to final delivery.